The Orton 3C was never designed with I/O in mind, other than serial via the /INT and A15 lines. The fact that it can work with regular I/O modules is fantastic, although there are some side effects. The 3C-PO shim gets over these issues.
Click the image above to open pdf schematic
When a read from a port is carried out, the Z80 asserts the /IORQ and /RD pins, and puts the port address on the address bus. The I/O module being addressed then puts its data on to the data bus for the Z80 to read. This is all fine.
When writing to a port, things can get a bit messy. The /IORQ and /WR pins are asserted, Register C, the port address, is put on the lower half of the address bus (A0 – A7), the contents of Register B register are put on the upper half of the address bus (A8 – A15), and the data is put on the data bus. This data will be taken by whichever I/O device is being addressed. This is all fine too.
However, despite the RAM needing /MREQ to be asserted to do a memory read, this is not used for a memory write. So any write to an I/O port will also result in a write to memory!
This isn’t as bad as it seems though. Due to the nature of the Orton C3, programs are likely to be very small as they are toggled in, so random writes in the address space probably won’t hit the code. With one exception – Address 0x0000. If the Front Panel I/O Module is being used, this uses address 0x00. So if the B register is either 0x00 or 0x80, and a write is made to the Front Panel I/O Module, then memory address 0x0000 will be overwritten with that data.
This is easy to work around by putting a NOP in 0x0000 and starting your code at 0x0001 if you are using the Front Panel I/O module. Alternatively, setting any number in Register B bigger than the size of your code will mean that random writes will be high enough in memory that you don’t need to worry.
For larger programs, other I/O modules, or code that actively uses Register B, random memory writes are more likely to be an issue. That’s where this shim, the Orton 3C-Plus Output, comes in.
The front panel of the Orton 3C generates a Write Enable (/WE) signal under two conditions; When the Cycle switch is pushed and the Write switch is active, or in RUN mode whenever the CPU asserts the /WR signal. This /WE signal connects through to the RAM to enable it to be written to.
This shim sits between the front panel and the backplane holding the CPU/RAM module and intercepts the /WE signal. The NOR gates will pass on the /WE signal if, and only if, /WE comes from the front panel and the /WAIT signal is asserted (manually toggling data in to RAM), or /WE comes from the front panel and the /MREQ is asserted (normal memory write in RUN mode).
Assembly
Building this should be easy if you have already built your Orton 3C. Just ensure that the orientation of the chip is correct, and that the 40 way socket goes towards the front panel and the 40 pin header goes towards the backplane containing the CPU/RAM module.
There is an unused gate on the ’02 chip. You probably won’t ever need this for anything. However, both of its inputs are connected to ground via a cuttable link to make it easy to isolate this and use it if you want.
Bill of Materials
1 Orton 3C-PO PCB
1 40 pin RA header
1 40 way RA socket
1 14 DIP socket
1 74HCT02
1 100nf