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Decoding ROM labels

Back in the earliest days of the RC2014, it came with a pre-programmed 27C512 64k ROM, with Microsoft BASIC on it in the first 8k, and it would work with 32k of RAM and a 68B50 ACIA.  One set up, one ROM, life was simple!

As time has gone on, and more options have become available, other ROM images, such as Microsoft BASIC for 56k RAM, CP/M Monitor, RomWBW and Small Computer Monitor have been introduced.  See this page for a brief overview of each option

Future possibilities, such as other UARTs, different CPUs or other variations will inevitably lead to more ROM images being needed.  So, in order to keep track of what is programmed where, ROMs are now being shipped out with a label on them.

27C512 64k ROM

Every 64k ROM now has an 8 digit code on it.  Each digit, from left to right, refers to an 8k bank from 0x0000 to 0xD000.  This bank can be selected with the A13, A14, A15 jumpers;

AddressA15A14A13ROM Label
0000000 Xooooooo
2000001 oXoooooo
4000010 ooXooooo
6000011 oooXoooo
8000100 ooooXooo
A000101 oooooXoo
C000110 ooooooXo
E000111 oooooooX

The value of the digit represents the ROM image that sits in that particular 8k bank.  Currently, it will be one of the following;

0 – Empty bank, available for user to program

R – Microsoft BASIC, for 32k RAM, 68B50 ACIA, with origin 0x0000

K – Microsoft BASIC, for 56k RAM, 68B50 ACIA, with origin 0x0000

1 – CP/M Monitor, for pageable ROM, 64k RAM, 68B50 ACIA, CF Module at 0x10, with origin at 0x0000

2 – Microsoft BASIC, for 32k RAM, SIO/2, with origin 0x0000

4 – Microsoft BASIC, for 56k RAM, SIO/2, with origin 0x0000

6 – CP/M Monitor, for pageable ROM, 64k RAM, SIO/2, CF Module at 0x10, with origin at 0x0000

88 – Small Computer Monitor for pageable ROM, 64k RAM, SIO/2 or 68B50 ACIA, with Microsoft BASIC and CP/M boot options [Note that this is a 16k image, so Page Size needs to be set to 16k and only A14 and A15 jumpers to select]

9 – Small Computer Monitor for any ROM, any RAM, any UART

Mini II

To further complicate things, the Mini II ships with an ST39SF010 – a 128k Flash RAM which is divided up in to 8 x 16k pages, or 16 x 8k pages, or some combination of those. There are different options for BASIC, SCM CP/M and also FORTH.

Chips are labelled as “M2 1.2”

ST39SF040 512k RomWBW 2.9.1

Version 2.9.1 of RomWBW needed to be compiled differently, based on what peripherals were to be supported.  To indicate which peripherals the ROM had support for, the designation of x.512K is used, where x is the software designation.

1.512k – RomWBW RC_Std.ROM 2.9.0

2.512k – RomWBW RC_Std.ROM 2.9.0 With PPIDE

3.512k – RomWBW RC_Std.ROM 2.9.0 With RTC

4.512k – RomWBW RC_Std.ROM 2.9.0 With PPIDE and RTC

5.512k – RomWBW RC_Std.ROM 2.9.0 With WDC Floppy

6.512k – RomWBW RC_Std.ROM 2.9.0 With WDC Floppy and PPIDE

7.512k – RomWBW RC_Std.ROM 2.9.0 With WDC Floppy and RTC

8.512k – RomWBW RC_Std.ROM 2.9.0 With WDC Floppy, PPIDE and RTC

ST39SF040 512k RomWBW 3.0 onwards

Since the release of RomWBW 3.0.0, peripherals are automatically detected, so there is no need for different builds.  Therefore the label will just indicate the revision programmed.  At the time of writing, as indicated above, the latest stable release is 3.0.2

As more ROM images are added, this list will be updated.

Standard factory ROM images can be downloaded from Github https://github.com/RC2014Z80/RC2014/tree/master/ROMs/Factory

Note that despite having total control over which designation I want to use for whichever ROM image and where that is located on the ROM – I still managed to pick a combination that my label gun was unable to do!  So some people will have a label that starts with an interlocking “n” and “u” character, which is the closest I could do to represent a “2”.  If this is the case, your “¬4006000” is actually “24006000”.  In order to get around this, I have now bought an extra 2 label guns, which have been dismantled to allow the belts to be swapped around, and reassembled.  Normally reassembly of label guns is only possible by a highly skilled and qualified octupus, so I don’t recommend anybody tries doing this themselves!

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Peripheral Addressing

The RC2014 currently uses a very simple, although inefficient method of addressing peripherals.  Most of the expansion modules feature a 74HCT138 used to provide up to 8 enable lines from 3 address signals.  For the purposes of this document, I will mainly refer to the Digital I/O Module, but the principals apply to all modules with a 74HCT138 (generally referred to simply as ‘138)

It is worth noting that the Z80 CPU can address up to 256 Input or 256 output addresses.  These are selected by the first 8 address lines (A0 – A7), IORQ going low and either WR or RD going low.

The ’138 has 3 enable pins, G1, G2B, G2A, all of which need to be true (G1 needs to be high, and both G2B and G2A need to be low) for the ‘138 to be enabled.  When it is enabled, the 3 address lines, A0, A1, A2 are read.  These 3 addresses have 8 possible combinations (000, 001, 010, 011, 100, 101, 110, 111), which will activate one of the 8 outputs Y0 to Y7.

In the Digital I/O Module, the ‘138 is activated when M1 is high, IORQ is low and A7 is low.  This corresponds to any port from 0 to 127 (IORQ being low indicates the address bus represents port, and A7 being low indicates the address bus is lower than 127).  [Side note – Serial I/O Module uses addresses 128 and 129, which are indicated by A7 being high].

The Z80 address pins A0 and A1, along with WR are connected to the address pins A0, A1, A2 on the ‘138.  This gives 4 addresses (00, 01, 10, 11) with the write bit high, and 4 with it low.

In normal use, the ports are addressed as 0 (In 0 or Out 0) on the Digital I/O Module.  (Or port 0, 1, 2 on the Digital Input module, for example).  However, any address that has A0, A1 and A7 low will work; 0—–00.  So echoes of this will appear on 4, 8, 12… 124.  So, whilst this works, and is fine for a small system without much I/O requirements, it quickly becomes inefficient as you need more ports.  In particular, it will clash with the Compact Flash Storage Module, which can have an impact on running CP/M.

In an ideal world, every peripheral should have a unique address, and with a lot of digital logic, this is certainly possible to do.  However, it will add both complexity and cost as well as needing more board space.

The easy solution, however, involves just 6 diodes and a resistor.  By connecting address lines A2 – A7 to the anode of each diode and the cathode of each diode to the G2A enable pin on the ‘138, any address above 00000011 will prevent the ‘138 from being enabled.  Effectively all the diodes are acting as a very simple OR gate.  A 10k resistor will bias the output low.

So with this set up, it will give just 4 unique addresses; 00000000, 00000001, 00000010, 00000011 (ie 0, 1, 2, 3) which for the Digital I/O Module, or the Digital Input or Digital Output is ideal.

Other addresses can be selected by changing which address pin the diodes are connected to.  So, for example, if A1 was connected to a diode instead of A3, and A3 went to the ‘138, the addresses would be 00000000, 00000001, 00001000, 00001001 (ie 0, 1, 8, 9).  Whilst it cuts down on the echoes at higher addresses, it’s still not perfect – but much better and still very cheap with minimal extra board space needed.

The Digital I/O Module has now been updated to reflect this change.  As PCB stocks run low on other modules, they too will have similar updates.  If you already have a non-diode selectable module, and wish to implement this, it is actually very simple to do as shown below.

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